NVIDIA
Built from 9 candidate reports with 28 first-hand accounts, covering 2026-27, 2025-26, 2024-25, 2023, 2021-22, 2021, 2020-21.
Hiring process
Roles: System Software Intern- 1
Online test
Online assessment: MCQs onlyHackerRank60 min35 questionsNegative marking for wrong answers (rate not stated)easySection Qs Min Topics MCQ 35 - C/C++ fundamentals, pointers, memory management, OOP, Python (NumPy), OS, aptitude, geometry, scenario judgement C/C++ · OOP · OS · Python · aptitude
Described as easy-to-medium. One account says the stated limit was 45 min while the platform allowed 60; modal value 60. Candidates stress C, C++ and Python OOP.
- 2
Technical interview
Technical interview with behavioural questionsHackerRank60 minproject architecture · mutex usage · runtime polymorphism · virtual functions · copy constructor · RAII and move semantics · padding and alignment · vtable · scheduling · kernel vs user mode · Docker vs VM · pointer bugs · stack-based DSA · ML basics
One round, about 1 h (extended 10 min in one account). Two kind interviewers. A few behavioural questions in between and at the end; role preference between systems and AI questioned.
Advice from candidates
153 pieces of advice, in their own words. Names removed.
Online Assessment is basically a race with time. Be very choosy, you roughly have 2.5 mins each question. Don't get stuck on one question and waste your time. Read a question for 1 Minute, if not able to think through it move to the next one.
online_test · 2025-26
Have a good understanding of STA, DS, VLSI and Computer Architecture.
online_test · 2025-26
You can solve aptitude problems from indiabix or any other websites available.
online_test · 2025-26
Can learn STA from youtube videos of Digital IC Design, [creator] or vlsiexpert.
online_test · 2025-26
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Question patterns reported
The kind of problem, not the problem itself. Our practice questions are written to match these patterns.
- OnlineFIFO minimum depth from differing read and write rates
- Onlinecache field widths in a non-binary address system
- Onlineclock-gating current readings to find leakage power
- Onlineoutput of faulty gcd code
- Onlinebuild large mux from 2:1 muxes and find delay
- Onlineinstruction fusion versus clock period tradeoff
- Onlinecounter value at given clock cycle with periodic reset
- Technicalwrite Verilog for Fibonacci sequence with few registers
- Technicalsize input FIFOs under priority and round-robin arbiters
- Technicalflip a given bit of stored data in hardware or Verilog
- Technicalmake a 3-input NAND from 2-input NANDs
- Technicalconvert a near-palindrome string into a palindrome
- Technicalchoose test data to detect swapped bits in memory
- Technicalverify an arbiter design
- Technicaltoggled doors puzzle, which remain open
- Technicalearliest valid timestamp using each digit once
- Technicalkth lexicographic permutation without enumeration
- Technicalsequence sum inequality to bound its length
- TechnicalLED stays on after first clock edge, in Verilog
- Technicaldecimal to two's complement and why it is used
- Technicalconvert numbers between bases
- Technicalslow down blink frequency using counter-based clock divider
- Technicalprobability of knight leaving board after m moves, DP
- Technicalspot and fix a memory bug in a short C program