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dronacharya.ai

NXP Semiconductors

PlacementSoftwareHardware and VLSI

Built from 1 candidate report with 2 first-hand accounts, covering 2022.

Hiring process

  1. 1

    Technical interview

    Interview round
    60 minvirtual

    C, Java, Python concepts · linked lists · trees · matrix rotation · arrays · puzzles · DSA · resume projects

    Two interviewers. Candidate learned of selection right after and was called to HR the same day on short notice.

Advice from candidates

7 pieces of advice, in their own words. Names removed.

  • Do competitive programming, be comfortable with the concepts of programming languages(you work in), data structures, algorithms, operating systems, dbms. Also, practice writing code from scratch, on a blank screen/paper. Try writing complete code, from taking input, importing libraries, creating classes, to generating output. Use platforms like gfg, leetcode, hackerrank, etc.

    preparation · 2022

  • While answering/coding any question in the interview, be verbal as much as you can. Tell the interviewer what you are thinking, if you have any doubts and how are you reaching the solution. This will help the interviewer know your thought process and will be beneficial in case your answer in correct. Work on your body language and be confident while answering.

    interview · 2022

  • After the technical interview, I got to know I was selected and called for the HR round on very short notice(it was not mentioned that it will happen on the same day). So be prepared mentally for such situations, handle them and don’t panic.

    HR · 2022

  • As this was a core company for me I just revised the concept taught in the course VLSI Design and IC design lab.

    preparation · 2022

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Question patterns reported

The kind of problem, not the problem itself. Our practice questions are written to match these patterns.

  • Technicallive coding on shared screen from scratch, 2-3 questions per language
  • Technicalcheck whether setup or hold is violated, then mitigation techniques
  • TechnicalCMOS NAND and NOR gate design and preference